AlteraNIOS II Processor
ARCHITECTURE
DESIGN OF HARDWARE
Processor hardware is basically divided into 5 parts
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Instruction Fetch Stage
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Instruction Decode Stage
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Execute Stage
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Memory Access Stage
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Write Back Stage
Instruction Fetch Stage (IF)
In this stage, the content of the Program Counter is used to access memory and fetch the next instruction to be executed.
Instruction Decode Stage (ID)
During this stage, the instruction is decoded and the required operands are retrieved from the general purpose registers (GPRs) or special function registers (SFRs).
Execute Stage (EX)
Any calculations are performed during this stage. This includes effective address calculation for Load or Store instructions. The next Program Counter value is also calculated during this stage of the pipeline so that branches, where applicable, can be executed. Some initial pre-calculation for memory decoding is also performed in this stage.
Memory Access Stage (MA)
If the instruction being executed is of the Load or Store variety, then the data memory is accessed during this stage. The previously calculated effective address is applied to the data memory and the read or write is performed in accordance with the instruction type.
Write Back Stage (WB)
During this stage, the results of the calculation from the Execute stage, or the memory load from the Memory Access stage, are updated into the general purpose registers or special function registers.
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Pipelined Hardware
Hardware has been pipelined to achieve optimum performance. This technique of pipelining allows simultaneous execution of a number of different instructions, each instruction being at a different stage in the pipeline.
Hazards introduced due to pipelined architecture
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Data Hazard - It occurs when the current instruction requires the result of a preceding instruction, but there are insufficient segments in the pipeline to compute the result and write it back to the register file in time for the current instruction to read that result from the register file.
To overcome this we have introduced stall cycles. Stalling delays the execution of the current instruction until the required operand is written to the register file. But this decreases pipeline efficiency and throughput.
Control Hazard
Control hazards take place when the processor needs to branch for example, if a definite condition is true, then jump from one part of the instruction stream to another, not essentially to the next instruction sequentially. In such type of case, the processor unable to tell in advance whether it should process the next instruction causing a control hazard.
To overcome control hazard we have re-arranged the sequence of instructions.
5 Stage Pipe Line
NOTE:
All the variables have separate indexes associated with them.
Hence, Variables with index 1 are executed in 1st cycle, index 2 in 2nd cycle, index 3 in 3rd cycle, index 4 in 4th cycle and with index 5 in 5th cycle.
dpsum18 is the final output which is fetched from register r5_18 in last step.
Data Conversion Table
Memory Location & Error Data
